CS-302 Quiz OnlineTest

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VU CS-302 Online Test Preparation

CS-302 Quiz Preparation Virtual University

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  • Total Questions10

  • Time Allowed10

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ClassName Chapter Wise Test

Here is List Of ClassName Chapter Wise Tests

Ch. # Test Name MCQs Available PDF File Answers Mode Launch Test
1 CS-302 Quiz Preparation Virtual University 147 Download PDF MCQ Answers Launch Test

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CS-302 Quiz Preparation Virtual University (MCQs With Answers)

Sr. # Questions Answers Choice
1 The three fundamental gates are ___________ AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND
2 A transparent mode means _____________. The changes in the data at the inputs of the latch are seen at the output The changes in the data at the inputs of the latch are not seen at the output Propagation Delay is zero (Output is immediately changed when clock signal is applied) Input Hold time is zero (no need to maintain input after clock transition)
3 The _____________ input overrides the ________ input. Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE)
4 in ____________, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access None of given options
5 ______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output Resolution Accuracy Quantization Missing Code
6 74HC163 has two enable input pins which are _______ and _________ ENP, ENT ENI, ENC ENP, ENC ENT, ENI
7 DRAM stands for __________ Dynamic RAM Data RAM Demoduler RAM None of given options
8 The OR Gate performs a Boolean _______ function Addition Subtraction Multiplication Division
9 Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 Q2:= Q1 & X & Q3 Q2:= Q1 ! X ! Q3
10 In the following statement Z PIN 20 ISTYPE „reg.invert‟; The keyword “reg.invert” indicates ________ An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output
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