More Classes
5th Class
6th Class
7th Class
8th Class
9th Class
10th Class
11th Class
12th Class
NAT I
NAT II
CSS
IQ
General Knowledge
MDCAT
ECAT
GAT General
GAT Subject
Other Links
Go to Home
Online Tests
CS-302 Quiz Preparation Virtual University MCQs With Answers
Question # 1
The decimal “17” in BCD will be represented as _________
Choose an answer
11101
11011
10111
11110
Previous
Skip
Next
Question # 2
In order to synchronize two devices that consume and produce data at different rates, we can use _________
Choose an answer
Read Only Memory
Fist In First Out Memory
Flash Memory
Fast Page Access Mode Memory
Previous
Skip
Next
Question # 3
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?
Choose an answer
= 0, Cout = 0
= 0, Cout = 1
= 1, Cout = 0
= 1, Cout = 1
Previous
Skip
Next
Question # 4
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
Choose an answer
Set-up time
Hold time
Pulse Interval time
Pulse Stability time
Previous
Skip
Next
Question # 5
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____
Choose an answer
Zero
One
Undefined
No output as input is invalid
Previous
Skip
Next
Question # 6
74HC163 has two enable input pins which are _______ and _________
Choose an answer
ENP, ENT
ENI, ENC
ENP, ENC
ENT, ENI
Previous
Skip
Next
Question # 7
The sequence of states that are implemented by a n-bit Johnson counter is
Choose an answer
n+2 (n plus 2)
2n (n multiplied by 2)
2n (2 raise to power n)
n2 (n raise to power 2)
Previous
Skip
Next
Question # 8
In a sequential circuit the next state is determined by ________ and _______
Choose an answer
State variable, current state
Current state, flip-flop output
Current state and external input
Input and clock signal applied
Previous
Skip
Next
Question # 9
A transparent mode means _____________.
Choose an answer
The changes in the data at the inputs of the latch are seen at the output
The changes in the data at the inputs of the latch are not seen at the output
Propagation Delay is zero (Output is immediately changed when clock signal is applied)
Input Hold time is zero (no need to maintain input after clock transition)
Previous
Skip
Next
Question # 10
DRAM stands for __________
Choose an answer
Dynamic RAM
Data RAM
Demoduler RAM
None of given options
Previous
Skip
Next
Question # 11
Demultiplexer is also called.
Choose an answer
Data selector
Data router
Data distributor
Data encoder
Previous
Skip
Next
Back