VU CS-302 Online Test Preparation

CS-302 Quiz Preparation Virtual University

Sr. #	Questions	Answers Choice
1	For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will______ if the clock goes HIGH	toggle set reset not change
2	What is the difference between a D latch and a D flip-flop?	The D latch has a clock input The D flip-flop has an enable input The D latch is used for faster operation The D flip-flop has a clock input
3	The storage cell in SRAM is	a flip –flop a capacitor a fuse a magnetic domain
4	The 4-bit 2‟s complement representation of “+5” is _____________	1010 1110 1011 0101
5	FIFO is an acronym for __________	First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options
6	The alternate solution for a demultiplexer-register combination circuit is _________	Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register
7	________ is used to minimize the possible no. of states of a circuit.	State assignment State reduction Next state table State diagram
8	A synchronous decade counter will have _______ flip-flops.	3 4 7 10
9	74HC163 has two enable input pins which are _______ and _________	ENP, ENT ENI, ENC ENP, ENC ENT, ENI
10	____________ counters as the name indicates are not triggered simultaneously.	Asynchronous Synchronous Positive-Edge triggered Negative-Edge triggered