CS-302 Quiz Preparation Virtual University With Answers

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CS-302 Quiz Preparation Virtual University

Sr. # Questions Answers Choice
1 If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid Input is invalid
2 WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO. THE FLOP-FLOP IS TRIGGERED Q=0 AND Q‟=1 Q=1 AND Q’=0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
3 Sum term (Max term) is implemented using ________ gates OR AND NOT OR-AND
4 In designing any counter the transition from a current state to the next sate is determined by Current state and inputs Only inputs Only current state current state and outputs
5 The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms 4 8 12 16
6 Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer A parallel to serial converter circuit A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder
7 The power dissipation, PD, of a logic gate is the product of the dc supply voltage and the peak current dc supply voltage and the average supply current ac supply voltage and the peak current ac supply voltage and the average supply current
8 Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero. A = 1, B = 0, C = 0, D = 0 A = 1, B = 0, C = 1, D = 0 A = 0, B = 1, C = 0, D = 0 A = 1, B = 0, C = 1, D = 1
9 If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be set reset invalid clear
10 The OR gate performs Boolean ___________. multiplication subtraction division addition
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