Question # 1

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status

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3

7

8

15

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.

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10 Hz

50 Hz

100 Hz

500 Hz

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

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Undefined

One

Zero

No Output as input is invalid

NAND gate is formed by connecting _________

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AND Gate and then NOT Gate

NOT Gate and then AND Gate

AND Gate and then OR Gate

OR Gate and then AND Gate

The output of an XNOR gate is 1 when ____________ . I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.

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I Only

IV Only

I and IV only

II and III only

The total amount of memory that is supported by any digital system depends upon ______

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The organization of memory

The structure of memory

The size of decoding unit

The size of the address bus of the microprocessor

The design and implementation of synchronous counters start from _________

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Truth table

k-map

state table

state diagram

Flip flops are also called _____________

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Bi-stable dualvibrators

Bi-stable transformer

Bi-stable multivibrators

Bi-stable singlevibrators

74HC163 has two enable input pins which are _______ and _________

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ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

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