Question # 1

A decade counter is __________.

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Mod-3 counter

Mod-5 counter

Mod-8 counter

Mod-10 counter

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

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Set-up time

Hold time

Pulse Interval time

Pulse Stability time

If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)

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AND

OR

NOT

XOR

__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.

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Race condition

Clock Skew

Ripple Effect

None of given options

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

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Undefined

One

Zero

No Output as input is invalid

The simplest and most commonly used Decoders are the ______ Decoders

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n to 2n

(n-1) to 2n

(n-1) to (2n-1)

n to 2n-1

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

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GATED FLIP-FLOPS

PULSE TRIGGERED FLIP-FLOPS

POSITIVE-EDGE TRIGGERED FLIP-FLOPS

NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

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1

2

4

8

A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?

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= 0, Cout = 0

= 0, Cout = 1

= 1, Cout = 0

= 1, Cout = 1

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder

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AND

OR

NOT

XOR

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