CS-302 Quiz Preparation Virtual University With Answers

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CS-302 Quiz Preparation Virtual University

Sr. # Questions Answers Choice
1 The design and implementation of synchronous counters start from _________ Truth table state diagram k-map state table
2 THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________ GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
3 A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, Cout = 0 = 0, Cout = 1 = 1, Cout = 0 = 1, Cout = 1
4 The alternate solution for a multiplexer and a register circuit is _________ Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register
5 Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state Ten Eight Three Two
6 The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time
7 In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter
8 A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status 3 7 8 15
9 We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________ Using S-R Flop-Flop D-flipflop J-K flip-flop T-Flip-Flop
10 If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop 0 1 Invalid Input is invalid
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