Question # 1

DRAM stands for __________

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Dynamic RAM

Data RAM

Demoduler RAM

None of given options

____________ counters as the name indicates are not triggered simultaneously.

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Asynchronous

Synchronous

Positive-Edge triggered

Negative-Edge triggered

In order to synchronize two devices that consume and produce data at different rates, we can use _________

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Read Only Memory

Fist In First Out Memory

Flash Memory

Fast Page Access Mode Memory

5-bit Johnson counter sequences through ____ states

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7

10

32

25

The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines

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Write Time

Recycle Time

Refresh Time

Access Time

Stack is an acronym for _________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

The ABEL symbol for “OR” operation is

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!

&

#

$

RCO Stands for _________

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Reconfiguration Counter Output

Reconfiguration Clock Output

Ripple Counter Output

Ripple Clock Output

The _____________ input overrides the ________ input

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Asynchronous, synchronous

Synchronous, asynchronous

Preset input (PRE), Clear input (CLR)

Clear input (CLR), Preset input (PRE)

In a sequential circuit the next state is determined by ________ and _______.

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State variable, current state

Current state, flip-flop output

Current state and external input

Input and clock signal applied

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

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Doesn’t have an invalid state

Sets to clear when both J = 0 and K = 0

It does not show transition on change in pulse

It does not accept asynchronous inputs

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