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CS-302 Quiz Preparation Virtual University MCQs With Answers

Question # 1

The 4-bit 2‟s complement representation of “+5” is _____________

Choose an answer

1010

1110

1011

0101

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Question # 2

For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________

Choose an answer

Q(t)

Invalid

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Question # 3

The low to high or high to low transition of the clock is considered to be a(n) ________.

Choose an answer

State

Edge

Trigger

One-shot

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Question # 4

Given the state diagram of an up/down counter, we can find ________

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The next state of a given present state

The previous state of a given present state

Both the next and previous states of a given state

The state diagram shows only the inputs/outputs of a given states

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Question # 5

Stack is an acronym for _________

Choose an answer

FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

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Question # 6

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

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Question # 7

The output of an AND gate is one when _______

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All of the inputs are one

Any of the input is one

Any of the input is zero

All the inputs are zero

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Question # 8

74HC163 has two enable input pins which are _______ and _________

Choose an answer

ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

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Question # 9

What is the difference between a D latch and a D flip-flop?

Choose an answer

The D latch has a clock input

The D flip-flop has an enable input

The D latch is used for faster operation

The D flip-flop has a clock input

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Question # 10

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?

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Question # 11

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.

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