Question # 1

The low to high or high to low transition of the clock is considered to be a(n) ________.

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State

Edge

Trigger

One-shot

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

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GATED FLIP-FLOPS

PULSE TRIGGERED FLIP-FLOPS

POSITIVE-EDGE TRIGGERED FLIP-FLOPS

NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

A synchronous decade counter will have _______ flip-flops

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3

4

7

10

In asynchronous transmission when the transmission line is idle, _________

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It is set to logic low

It is set to logic high

Remains in previous state

State of transmission line is not used to start transmission

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

In designing any counter the transition from a current state to the next sate is determined by

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Current state and inputs

Only inputs

Only current state

current state and outputs

(A + B)(A + B + C)(A + C) is an example of ______________

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Product of sum form

Sum of product form

Demorgans law

Associative law

The decimal “17” in BCD will be represented as _________

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₁₁₁₀₁

11011

10111

11110

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

Smallest unit of binary data is a ________

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Bit

Nibble

Byte

Word

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series

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Low switching speeds, high power dissipation

Fast switching speeds, high power dissipation

Fast switching speeds, very low power dissipation

Low switching speeds, very low power dissipation

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