Question # 1

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

74HC163 has two enable input pins which are _______ and _________

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ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

If the FIFO Memory output is already filled with data then ________

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It is locked; no data is allowed to enter

It is not locked; the new data overwrites the previous data.

Previous data is swapped out of memory and new data enters

None of given options

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

In a sequential circuit the next state is determined by ________ and _______

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State variable, current state

Current state, flip-flop output

Current state and external input

Input and clock signal applied

The decimal “17” in BCD will be represented as _________

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₁₁₁₀₁

11011

10111

11110

Demultiplexer converts _______ data to __________ data.

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Parallel data, serial data

Serial data, parallel data

Encoded data, decoded data

All of the given options

If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)

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AND

OR

NOT

XOR

___________ is one of the examples of asynchronous inputs.

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J-K input

S-R input

D input

Clear Input (CLR)

The design and implementation of synchronous counters start from _________

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Truth table

k-map

state table

state diagram

The alternate solution for a multiplexer and a register circuit is _________

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Parallel in / Serial out shift register

Serial in / Parallel out shift register

Parallel in / Parallel out shift register

Serial in / Serial Out shift register

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