Question # 1

The design and implementation of synchronous counters start from _________

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Truth table

k-map

state table

state diagram

In asynchronous transmission when the transmission line is idle, _________

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It is set to logic low

It is set to logic high

Remains in previous state

State of transmission line is not used to start transmission

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.

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3

7

8

15

The sequence of states that are implemented by a n-bit Johnson counter is

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n+2 (n plus 2)

2n (n multiplied by 2)

2n (2 raise to power n)

n2 (n raise to power 2)

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

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1100

0011

0000

1111

Above is the circuit diagram of _______.

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Asynchronous up-counter

Asynchronous down-counter

Synchronous up-counter

Synchronous down-counter

74HC163 has two enable input pins which are _______ and _________

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ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

A transparent mode means _____________.

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The changes in the data at the inputs of the latch are seen at the output

The changes in the data at the inputs of the latch are not seen at the output

Propagation Delay is zero (Output is immediately changed when clock signal is applied)

Input Hold time is zero (no need to maintain input after clock transition)

The best state assignment tends to ___________.

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Maximizes the number of state variables that don’t change in a group of related states

Minimizes the number of state variables that don‟t change in a group of related states

Minimize the equivalent states

None of given options

The total amount of memory that is supported by any digital system depends upon ______

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The organization of memory

The structure of memory

The size of decoding unit

The size of the address bus of the microprocessor

The output of an AND gate is one when _______

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All of the inputs are one

Any of the input is one

Any of the input is zero

All the inputs are zero

Excess-8 code assigns _______ to “-8”

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1110

1100

1000

0000

In order to synchronize two devices that consume and produce data at different rates, we can use _________

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Read Only Memory

Fist In First Out Memory

Flash Memory

Fast Page Access Mode Memory

___________ is one of the examples of asynchronous inputs.

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J-K input

S-R input

D input

Clear Input (CLR)

The address from which the data is read, is provided by _______

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Depends on circuitry

None of given options

RAM

Microprocessor

Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________

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0000

1101

1011

1111

____________ counters as the name indicates are not triggered simultaneously.

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Asynchronous

Synchronous

Positive-Edge triggered

Negative-Edge triggered

LUT is acronym for _________.

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

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