Question # 1

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop

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0

1

Invalid

Input is invalid

The sequence of states that are implemented by a n-bit Johnson counter is

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n+2 (n plus 2)

2n (n multiplied by 2)

2n (2 raise to power n)

n2 (n raise to power 2)

Sum term (Max term) is implemented using ________ gates

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OR

AND

NOT

OR-AND

A frequency counter ______________

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Counts pulse width

Counts no. of clock pulses in 1 second

Counts high and low range of given clock pulse

None of given options

Stack is an acronym for_________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

74HC163 has two enable input pins which are _______ and _________

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ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

The simplest and most commonly used Decoders are the ______ Decoders

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n to 2n

(n-1) to 2n

(n-1) to (2n-1)

n to 2n-1

Excess-8 code assigns _______ to “-8”

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1110

1100

1000

0000

LUT is acronym for _________

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

____________ counters as the name indicates are not triggered simultaneously.

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Asynchronous

Synchronous

Positive-Edge triggered

Negative-Edge triggered

A synchronous decade counter will have _______ flip-flops.

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3

4

7

10

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