Question # 1

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

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Mod-6, Mod-10

Mod-50, Mod-10

Mod-10, Mod-50

Mod-50, Mod-6

___________ is one of the examples of asynchronous inputs.

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J-K input

S-R input

D input

Clear Input (CLR)

______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.

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Resolution

Missing Code

Accuracy

Quantization

LUT is acronym for _________

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

___________ is one of the examples of synchronous inputs.

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J-K input

EN input

Preset input (PRE)

Clear Input (CLR)

Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state

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Ten

Eight

Three

Two

The alternate solution for a demultiplexer-register combination circuit is _________

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Parallel in / Serial out shift register

Serial in / Parallel out shift register

Parallel in / Parallel out shift register

Serial in / Serial Out shift register

If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop

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0

1

Invalid

Input is invalid

A transparent mode means _____________.

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The changes in the data at the inputs of the latch are seen at the output

The changes in the data at the inputs of the latch are not seen at the output

Propagation Delay is zero (Output is immediately changed when clock signal is applied)

Input Hold time is zero (no need to maintain input after clock transition)

Stack is an acronym for _________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

Demultiplexer is also called.

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Data selector

Data router

Data distributor

Data encoder

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