Question # 1

The OR gate performs Boolean ___________.

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multiplication

subtraction

division

addition

____________ counters as the name indicates are not triggered simultaneously.

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Asynchronous

Synchronous

Positive-Edge triggered

Negative-Edge triggered

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status

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3

7

8

15

In order to synchronize two devices that consume and produce data at different rates, we can use _________

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Read Only Memory

Fist In First Out Memory

Flash Memory

Fast Page Access Mode Memory

Stack is an acronym for_________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be

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set

reset

invalid

clear

The basic building block for a logical circuit is _______

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A Flip-Flop

A Logical Gate

An Adder

None of given options

In ________ outputs depend only on the current state

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Mealy machine

Moore Machine

State Reduction table

State Assignment table

For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________

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0

1

Q(t)

Invalid

"A + B = B + A" is __________

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Demorgan‟s Law

Distributive Law

Commutative Law

Associative Law

LUT is acronym for ________.

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

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