Question # 1

The information is transferred from the ________ and_______ specified register.

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MDR

CPU

Both a and b

None

WE stand for

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Write enable

Wrote enable

Write envy

None

SI Stand for

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Stand Index

Source index

Segment index

Simple index

NMI stand for

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Non mask able interrupt

Non mistake interrupt

Both a and b

None

Power PC microprocessor architecture is developed by.

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Apple

IBM

Motorola

All these

CPU can read and write data by using.

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Control bus

Data Bus

Address bus

None

Intel Used HMOS technology to recreate _____

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8084 A

8085 A

8086 A

8088 A

Which are the categorized of Flag

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Conditional flag

Control flag

Both a and b

None

DMA Stand for

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Direct memory access

Direct memory allocation

Data memory access

Data memory allocation

Secondary memory can store.

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Program store code

Compiler

Operating system

All of these

Which is the most commonly measured in term of MIPS previously millions instructing peer second.

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Microprocesser

Performance of a microprocessor.

Assembly line

None

Which latch is mostly used creating memory register.

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SR-Latch

JK- Latch

D-Latch

T-Latch

Name of typical dedicated regtister.

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PC

IR

SP

All these

Which is a programmable communication interface.

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8255

8254

8251

8359

Which is not the control bus signal

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READ

WRITE

RESET

None

Which are the architectural paradigms in microprocessor.

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RISC

CISC

PISC

A and B

RD stand for

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Read

Register

Request

Real

How many types of microprocessor comprieses.

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3

6

4

9

The principal of working of the cache memory largely depends on which locality.

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Spatial locality

Temporal locality

Sequentially

All of these

How many type of cache memory

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1

2

3

4

The CU is designed by using which techniques.

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HARD WIRED CONTROLS

MICRO PROGRAMMIING

NANO PROGRAMMING

All of these

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PPSC Computer Science Chapter 17 Microprocessor And Assembly Language Online Test MCQs With Answers

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