Question # 1

Which RAM is created using MOS transistors.

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Dynamic RAM

Static RAM

Permanent RAM

SD RAM

The range of this rating for which microprocessor of.

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VLSI

Motorola

Intel

Zilog

Cache is usually the ______ of memory access by the microprocessor.

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First level

Second level

Third level

Fourth level

The ___________ of can assembly line to be 1/tp.

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Clock period

Pipelining

Through out

Flow thorugh

8254 gate of a counter is to either

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Enable counting

Disable counting

Both a and b

None

Power PC microprocessor architecture is developed by.

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Apple

IBM

Motorola

All these

How many speed of 8088 , 8085 , 8086 microprocessor.

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2.5 million instructions per second

1.5 Million instruction per second

3.5 Million instruction second

1.6 Million instruction per second

a 16 bit address bus can generate ________ address bus.

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16

32

36

64

___________ a sub system that transfer data between computer components inside a computer or between computer.

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Chip

Register

Bus

processor

ED stand for

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Enable MRD

Enable MDR

Both a and b

None

8254 programmable timer counter has two inputs signals.

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CLK

Gate

Both a and b

None

AL 7 99H which operation is performed here

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Input

Out put

Both a and b

None

IRR stand for

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Interrupt request register

Input request register

Input resolver register

Interrupt resolver register

When memory write or I/O read are active data is from the processor.

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Input

Out put

Processor

None

Which is widely used in interrupt controller with a number of microprocessor.

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8251

8254

8255

8259

BP stand for

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Bit pointer

Base pointer

Bus pointer

Byte pointer

VAM sand for

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Valid memory address

Virtual memory address

variable memory address

None

34 H& AX which operation is performed here

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Input

Output

Progress

None

Pentium pro processor contains

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L1 Cache

L2 cache

Both a and b

None

Secondary memory can store.

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Program store code

Compiler

Operating system

All of these

Which formula is used to calculate the number of write stall cycles.

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Reads * read miss rate* read miss penalty

write * write miss + Write buffer stalls

Memory access* cache miss rate * cache miss penalty

None

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