Question # 1

Which mode is used to double handshakes in 8255

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Mode 0

Mode 1

Mode 2

Mode 3

ISA stand for

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Instruct set area

Instruction set architecture

Both a and b

None

Which are the cache controller ports.

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64 bit AHB -Lite slave ports

64- bit AHB -Lite Master ports

Both a and b

None

Which are the flags of status register.

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Over flow flag

carry flag

Half carry flag

All of these

The time taken for all stages of the assembly line to become active is called the

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Flow through time

Clock period

Through put

All of these

Which memory is used to holds the address of the data stored in the cache.

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Associative memory

Case memory

Ordinary memory

None

Who is the represents the fundamental process in the operation of the CPU

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The fetch execute cycle and pipelining.

The assembly

Both a and b

None

MAR stand for

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Memory address register

Memory data recode

Micro data register

None

How many bit stored by status register

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1 bit

4 bit

6 bit

8 bit

Which is the professional or Business version of intel processor.

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Pentium II

Pentium pro

Pentium MMX

Pentium Xeon

Which are the four categories of registers.

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General purpose register

Pointer or index registers

Segment registers

All of these

Which is the components of computer

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System bus

CPU

Memory unit

All these

Which formula is used to calculate the number of read stall cycles.

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Reads read miss rate read miss penalty

Write +Wrier buffer stalls

Memory access* cache miss rate * cache miss penalty

None

Alpha AXP is developed by

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DEC

IBM

Motorola

Intel

Which microprocessor to read an item from memory.

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VAM

SAM

MOC

None

Which is not the main architectural feature of Power PC.

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It is not based on RISC

Superscalar implementation

Both 32 and 64 bit

Paged memory managemnet architecture

Which converter convert binary number into their equivalent voltages.

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Analogue to analogue

Analogue to digital

Digital to digital

Digital to analogue

The DMA controllers are specials hardware embedded into the chip in modern integrate processor that ____________ and _________ to the system.

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Data transfer

Arbitrate access

Both a and b

None

Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU.

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Control bus

Data bus

Address bus

None

Secondary memory is also called.

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Auxiliary

Backup store

Both a and b

None

Which are the architectural paradigms in microprocessor.

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RISC

CISC

PISC

A and B

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