Question # 1

in linear decoding address bus of 16 -bit wide can connect only of RAM

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Address map is not contiguous

Confects occur if two of the select lines become active at the same time

If all unused address lines are not used as chip selectors then these unused lines become don't cares.

None

CAD stand for.

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Computer aided drafting

Compare aided drafting

Both a and b

None

HMOS stand for

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High performance metal oxide semiconductor

High processor metal oxide semiconductor

Both a and b

None

Which are used DMA controllers with 8085/8086 microprocessor.

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8237

8357

Both a and b

None

AL 7 99H which operation is performed here

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Input

Out put

Both a and b

None

The left side of any binary number is called.

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Least significant digit

Most significant digit

Medium significant digit

Low significant digit

What is the period of fourth generation

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1979 - 1980

1981-1995

1995-2000

1974-1980

The growth of SSI up to.

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100 device on a chip

200 device on a chip

300 device on a chip

400 device on a chip

The principal of working of the cache memory largely depends on which locality.

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Spatial locality

Temporal locality

Sequentially

All of these

Which of some of popular processor.

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Motorola 6800 and 6809

Intel 8085

Zilog Z 80

All above

How many parts of single address computer instruction.

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1

2

3

4

The beginning of very efficient ______ microprocessor in second generation.

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4-bit

8-bit

16 -bit

64 -bit

How many architectural paradigms in microprocessor.

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2

3

4

6

Which is the small amount of highs speed memory used to work directly with the microprocessor

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Cache

Case

Cost

Coos

Name of typical dedicated regtister.

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PC

IR

SP

All these

Which register contains the 8086/8088 flag

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Status register

Stack register

Flag register

Stand register

Which is the part of memory unit

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Processor memory

Main memory

Secondary memory

All of these

Which is widely used in interrupt controller with a number of microprocessor.

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8251

8254

8255

8259

The DMA controllers are special hardware embedded into the chip in modern integrate processor that __________ and ________ to the system.

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Data transfer

Arbitrate access

Both a and b

None

When memory write or I/O read are active data is from the processor.

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Input

Out put

Processor

None

The offset of a particular segment varies from_______

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000H to FFFH

0000H to FFFFH

00H to FFH

00000H to FFFFFH

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