Question # 1

Direct mapping is a _____________ to implement cache memory

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Cheaper way

Case way

Cache way

None

Which is the types of cache memory

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Fully associative cache

Direct mapped cache

Set associative cache

All of these

Which is the most commonly measured in term of MIPS previously millions instructing peer second.

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Microprocesser

Performance of a microprocessor.

Assembly line

None

Which are used for port A in 8255 mode 1.

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PC0-PC2

PC3-PC7

PC6-PC7

PC3-PC5

Name of typical dedicated regtister.

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PC

IR

SP

All these

Third generation micro processor is dominated by _______ micro processor.

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8 bit

4 bit

16 bit

64 bit

_____ is the condiction

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CD

IR

Both a and b

None

Which mode is used to double handshakes in 8255

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Mode 0

Mode 1

Mode 2

Mode 3

Customized ROMS are called.

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Mask ROM

Flash ROM

EPROM

None

How many stages has fetch execute cycle.

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3

4

5

6

Micro processor is fabricated on single chip using.

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MOS

ALU

CPU

All of these

Which latch is mostly used creating memory register.

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SR-Latch

JK- Latch

D-Latch

T-Latch

RD stand for

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Read

Register

Request

Real

Which RAM is created using MOS transistors.

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Dynamic RAM

Static RAM

Permanent RAM

SD RAM

How many bit or MAR register

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8 bit

16 bit

32 bit

64 bit

_________ causes the address of the next microprocessor to be obtained from the memory.

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CRJA

ROM

MAP

HLT

WB stand for

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Write buffers

Written buffers

Wrote buffers

None

How many bit microprocessor developed by intel.

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4 bit

8 bit

32 bit

64 bit

The information is transferred from the ________ and_______ specified register.

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MDR

CPU

Both a and b

None

How many parts of single address computer instruction.

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1

2

3

4

PR stand for

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Priority register

Priority resolver

Priority request

None

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PPSC Computer Science Chapter 17 Microprocessor And Assembly Language Online Test MCQs With Answers

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